Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures.
Yong-Kyu JungPublished in: J. Signal Process. Syst. (2011)
Keyphrases
- hardware software
- multi core processors
- hardware and software
- signal processing
- hw sw
- field programmable gate array
- low cost
- embedded systems
- systolic array
- design methodology
- parallel computing
- high performance computing
- hardware implementation
- low complexity
- evolutionary algorithm
- parallel programming
- cloud computing
- functional units
- data processing
- general purpose