A Low-Power Delay Buffer Using Gated Driver Tree.
Po-Chun HsiehJing-Siang JhuangPei-Yun TsaiTzi-Dar ChiuehPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- power dissipation
- single chip
- buffer size
- high power
- logic circuits
- vlsi architecture
- digital signal processing
- image sensor
- cmos technology
- low power consumption
- wireless transmission
- loss probability
- vlsi circuits
- gate array
- power reduction
- mixed signal
- ultra low power
- nm technology
- video sequences
- index structure
- digital camera