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Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture.
R. Udaiyakumar
Senoj Joseph
T. V. P. Sundararajan
Dhasarathan Vigneswaran
R. Maheswar
Iraj S. Amiri
Published in:
Wirel. Pers. Commun. (2018)
Keyphrases
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low power
power consumption
power reduction
vlsi architecture
logic circuits
power dissipation
high speed
cmos technology
low cost
power management
delay insensitive
nm technology
mixed signal
single chip
energy efficiency
vlsi implementation
power saving
pattern recognition
signal processor
low power consumption
real time
digital signal processing
energy saving
gate array
ultra low power