Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture.
R. UdaiyakumarSenoj JosephT. V. P. SundararajanDhasarathan VigneswaranR. MaheswarIraj S. AmiriPublished in: Wirel. Pers. Commun. (2018)
Keyphrases
- low power
- power consumption
- power reduction
- vlsi architecture
- logic circuits
- power dissipation
- high speed
- cmos technology
- low cost
- power management
- delay insensitive
- nm technology
- mixed signal
- single chip
- energy efficiency
- vlsi implementation
- power saving
- pattern recognition
- signal processor
- low power consumption
- real time
- digital signal processing
- energy saving
- gate array
- ultra low power