Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design.
Jaydeep KulkarniThomas F. WenischPublished in: IEEE Des. Test (2018)
Keyphrases
- low power
- international symposium
- single chip
- low cost
- power consumption
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- gate array
- digital signal processing
- computational intelligence
- revised papers
- cmos technology
- context aware
- power reduction
- mixed signal
- power dissipation
- real time
- ultra low power
- ambient intelligence