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A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM.
Hiroaki Nambu
Kazuo Kanetani
Kaname Yamasaki
Keiichi Higeta
Masami Usami
Yasuhiro Fujimura
Kazumasa Ando
Takeshi Kusunoki
Kunihiko Yamaguchi
Noriyuki Homma
Published in:
IEEE J. Solid State Circuits (1998)
Keyphrases
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power consumption
cmos technology
high speed
low power
nm technology
random access memory
low cost
access control
power dissipation
low voltage
parallel processing
times faster
vlsi circuits
real time
data transmission
power management
power reduction