A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS.
Cihun-Siyong Alex GongCi-Tong HongKai-Wen YaoMuh-Tian ShiuePublished in: APCCAS (2008)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- cmos technology
- high power
- wireless transmission
- low power consumption
- digital signal processing
- vlsi circuits
- power saving
- vlsi architecture
- image sensor
- power reduction
- mixed signal
- gate array
- ultra low power
- logic circuits
- power dissipation
- nm technology
- power management