Model Checking of Embedded Systems Using RTCTL While Generating Timed Kripke Structure.
Yajun WuSatoshi YamanePublished in: COMPSAC (1) (2018)
Keyphrases
- model checking
- embedded systems
- timed automata
- temporal logic
- partial order reduction
- finite state machines
- verification method
- formal verification
- finite state
- symbolic model checking
- temporal properties
- low cost
- model checker
- computation tree logic
- real time systems
- reachability analysis
- embedded devices
- automated verification
- formal specification
- embedded software
- transition systems
- pspace complete
- asynchronous circuits
- bounded model checking
- process algebra
- epistemic logic
- concurrent systems
- reactive systems
- field programmable gate array
- modal logic
- petri net
- real time
- formal methods
- deterministic finite automaton
- multi agent
- alternating time temporal logic
- artificial intelligence