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Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm.
Honghong Long
Yu Bai
Yanze Li
Jian Wang
Jinmei Lai
Published in:
ASICON (2023)
Keyphrases
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simulated annealing algorithm
simulated annealing
high speed
test data generation
genetic algorithm
hardware implementation
search algorithm
low cost
signal processing
field programmable gate array
real time
hardware architecture
real time image processing
annealing algorithm
verilog hdl
fpga implementation