A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS.

Wanghua Wu Xuefei Bai Robert Bogdan Staszewski John R. Long

Published in: ISSCC (2013)

Keyphrases

metal oxide semiconductor
high speed
circuit design
power consumption
low cost
cmos technology
integrated circuit
cmos image sensor
silicon on insulator
low power
nm technology
vlsi circuits
high frequency
differential equations
fractional order
analog vlsi