Low power level shifter and combined with logic gates.

Ko-Chi Kuo Sheng-Quane Chen

Published in: APCCAS (2010)

Keyphrases

low power
logic circuits
power consumption
low cost
high speed
single chip
delay insensitive
high power
wireless transmission
vlsi architecture
gate array
low power consumption
power dissipation
image sensor
vlsi circuits
cmos technology
real time