Counterexample Generation for Probabilistic Timed Automata Model Checking.
Junhua ZhangZhiqiu HuangZining CaoFangxiong XiaoPublished in: CSSE (2) (2008)
Keyphrases
- model checking
- timed automata
- temporal logic
- reachability analysis
- formal verification
- finite state
- temporal properties
- model checker
- finite state machines
- formal specification
- partial order reduction
- symbolic model checking
- automated verification
- bounded model checking
- formal methods
- epistemic logic
- probabilistic model
- verification method
- process algebra
- computation tree logic
- bayesian networks
- transition systems
- pspace complete
- linear temporal logic
- concurrent systems
- asynchronous circuits
- deterministic finite automaton
- conditional probabilities
- real time