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A low-power hybrid reconfigurable architecture for resistive random-access memories.
Miguel Angel Lastras-Montaño
Amirali Ghofrani
Kwang-Ting Cheng
Published in:
HPCA (2016)
Keyphrases
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low power
random access
reconfigurable architecture
low cost
power consumption
high speed
systolic array
solid state
single chip
low power consumption
image sensor
flash memory
cmos technology
vlsi circuits
gate array
logic circuits
mixed signal
power dissipation