A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC.
Wei GuoShahriar MirabbasiPublished in: ISCAS (2012)
Keyphrases
- low power
- analog to digital converter
- mixed signal
- high speed
- single chip
- power consumption
- low cost
- image sensor
- vlsi circuits
- high power
- sar images
- wireless transmission
- digital signal processing
- image reconstruction
- power supply
- logic circuits
- vlsi architecture
- low power consumption
- cmos image sensor
- transmission line
- delay insensitive
- hardware and software
- power dissipation