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A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform.
Florian Eibensteiner
Jürgen Kogler
Josef Scharinger
Published in:
CVPR Workshops (2014)
Keyphrases
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hardware architecture
stereo vision
hardware implementation
learning algorithm
preprocessing
computational complexity
post processing
stereo images
depth information
field programmable gate array
hardware architectures
disparity map
parallel implementation