A novel design technique for very low voltage MOS translinear circuits.

Antonio J. López-Martín Alfonso Carlosena Jaime Ramírez-Angulo

Published in: ISCAS (1) (2003)

Keyphrases

power consumption
cmos technology
low voltage
power dissipation
low power
mixed signal
floating gate
high speed
power line
neural network
design considerations
real time
design process