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A novel design technique for very low voltage MOS translinear circuits.
Antonio J. López-Martín
Alfonso Carlosena
Jaime Ramírez-Angulo
Published in:
ISCAS (1) (2003)
Keyphrases
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power consumption
cmos technology
low voltage
power dissipation
low power
mixed signal
floating gate
high speed
power line
neural network
design considerations
real time
design process