The asynchronous counterflow pipeline bit-serial multiplier.

Milorad B. Tosic Mile K. Stojcev Dejan M. Maksimovic Goran Lj. Djordjevic

Published in: J. Syst. Archit. (1998)

Keyphrases

shift register
hardware implementation
application specific
pipeline architecture
bit vectors
random access memory
artificial intelligence
floating point
type ii
real time
social networks
knowledge base
discussion forums
error correcting codes
asynchronous communication
magnetic tape