Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
Yiran ChenHai LiCheng-Kok KohGuangyu SunJing LiYuan XieKaushik RoyPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
- low power
- logic circuits
- power dissipation
- power consumption
- high speed
- low cost
- nm technology
- digital signal processing
- gate array
- data flow
- vlsi architecture
- single chip
- cmos technology
- high power
- low power consumption
- vlsi circuits
- power reduction
- signal processor
- response time
- power saving
- energy dissipation
- signal processing