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Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique.

I-Chyn WeyChun-Wei ChangYu-Cheng LiaoHeng-Jui Chou
Published in: Int. J. Circuit Theory Appl. (2015)
Keyphrases
  • noise tolerant
  • circuit design
  • high speed
  • power consumption
  • chip design
  • power dissipation
  • single phase
  • active power filter
  • cmos technology
  • noisy data