FPGA acceleration of Sparse Matrix-Vector Multiplication based on Network-on-Chip.
Hong-Yuan JhengC. C. SunShanq-Jang RuanJürgen GötzePublished in: EUSIPCO (2011)
Keyphrases
- sparse matrix
- network on chip
- floating point
- routing algorithm
- multi processor
- network simulator
- data transfer
- hardware implementation
- high speed
- random projections
- fixed point
- hardware design
- power dissipation
- pattern recognition
- interconnection networks
- shared memory
- data sets
- program execution
- signal processing
- low cost
- objective function