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Five-Stage, Power Efficient, Dual Rail, 100MHz, 10dB Programmable Gain Amplifier with Down-Stepping Functions in 28nm CMOS.

Vahur KampusRobert TeschnerUlrich GaierThomas LinderGerhard NössingMartin Trojer
Published in: ISCAS (2019)
Keyphrases
  • high speed
  • power consumption
  • low power
  • cmos technology
  • high power
  • low cost
  • nm technology
  • cost effective
  • database
  • single chip
  • data sets
  • image processing
  • parallel computing
  • power supply
  • power dissipation