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High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA.
Anissa Sghaier
Zeghid Medien
Loubna Ghammam
Sylvain Duquesne
Mohsen Machhout
Hassan Yousif Ahmed
Published in:
Microprocess. Microsystems (2018)
Keyphrases
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high speed
real time
data acquisition
efficient implementation
low power
bayesian networks
hardware implementation
worst case
single chip
parallel architecture
gate array
b spline
fpga device
xilinx virtex
fpga technology