Design of a low power network interface for Network on chip.

K. Swaminathan G. Lakshminarayanan Frank Lang Maher Fahmi Seok-Bum Ko

Published in: CCECE (2013)

Keyphrases

low power
power dissipation
network on chip
power consumption
single chip
cmos technology
low power consumption
high speed
low cost
vlsi architecture
logic circuits
packet switched
digital signal processing
gate array
routing algorithm
real time
image sensor
network traffic
network structure
design process