Design of FFT processor using low power Vedic multiplier for wireless communication.
C. PadmaP. JagadambaP. Ramana ReddyPublished in: Comput. Electr. Eng. (2021)
Keyphrases
- low power
- single chip
- wireless communication
- high speed
- gate array
- power consumption
- low cost
- low power consumption
- wireless transmission
- digital signal processing
- vlsi architecture
- logic circuits
- cmos technology
- power reduction
- mixed signal
- power dissipation
- real time
- computer simulation
- wireless sensor networks
- ultra low power
- image sensor
- floating point
- wireless channels
- embedded systems
- nm technology
- wireless networks
- short range
- mobile communication
- hardware implementation
- communication networks
- sensor networks