Fault-tolerant VLSI processor array for the SVD.
Joseph R. CavallaroChristopher D. NearM. Ümit UyarPublished in: ICCD (1989)
Keyphrases
- processor array
- fault tolerant
- singular value decomposition
- fault tolerance
- parallel implementation
- parallel algorithm
- distributed systems
- mesh connected
- load balancing
- least squares
- dimensionality reduction
- parallel computers
- state machine
- safety critical
- massively parallel
- linear algebra
- principal component analysis
- color images
- mobile agent system
- array processor