Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator.
Anuar JaafarNorhayati SoinSharifah Wan Muhamad HattaSani Irwan Md. SalimPublished in: IET Comput. Digit. Tech. (2019)
Keyphrases
- field programmable gate array
- hardware implementation
- programmable logic
- embedded systems
- parallel computing
- hardware architecture
- digital signal processors
- image processing algorithms
- fpga device
- hardware design
- computing systems
- digital signal processing
- hardware software
- software implementation
- limit cycle
- information systems
- fine grained
- reconfigurable hardware
- massively parallel
- low power consumption
- clock frequency
- host computer
- fpga technology
- hardware software co design
- neural network
- real time
- efficient implementation
- pattern recognition
- hw sw
- pipelined architecture