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Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture.
Yixuan Zhang
Randy Wayne Morris Jr.
Avinash Karanth Kodi
Published in:
Microprocess. Microsystems (2011)
Keyphrases
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network on chip
power dissipation
packet switched
power consumption
multi processor
routing algorithm
network simulator
low power
design methodology
cmos technology
high speed
data transfer
embedded systems
digital signal processing
simulation environment
scheduling algorithm
design process
image processing