A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation.
Seyed Alireza ZahraiMarina ZlochistiNicolas Le DortzMarvin OnabajoPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
- low power
- high speed
- single chip
- low cost
- power consumption
- digital signal processing
- high power
- real time
- wireless transmission
- low power consumption
- logic circuits
- vlsi architecture
- gate array
- vlsi circuits
- efficient implementation
- power dissipation
- power reduction
- image sensor
- frame rate
- analog to digital converter