Systolic Architecture of Adaptive Post Detection Integration CFAR Processor in Binomial Distribution Pulse Jamming.
Ivan GarvanovChristo A. KabakchievPlamen DaskalovPublished in: LSSC (2003)
Keyphrases
- systolic array
- target detection
- false alarm rate
- false alarms
- detection algorithm
- detection rate
- management system
- false positives
- parallel architecture
- software architecture
- detection method
- object detection
- multi processor
- data flow
- instruction set
- automatic detection
- real time
- loose coupling
- memory management
- industry standard
- generalized likelihood ratio
- computation intensive
- matched filter
- content management
- learning capabilities
- high speed
- anomaly detection