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Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding.
Myung-Suk Byeon
Yil-Mi Shin
Yong-Beom Cho
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
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hardware architecture
avc video coding
rate control
intra prediction
hardware implementation
hardware architectures
rate distortion optimization
rate distortion
associative memory
neural network
bit rate
mode decision
parallel algorithm
video streaming
signal processing
peer to peer
support vector