Hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress.
Sena HounsinouAishwarya VasuHarini RamaprasadPublished in: CODES+ISSS (2018)
Keyphrases
- hardware implementation
- signal processing
- efficient implementation
- dedicated hardware
- hardware design
- software implementation
- hardware architecture
- image processing algorithms
- fpga implementation
- field programmable gate array
- parallel architecture
- memory management
- pipeline architecture
- computer vision
- pattern recognition
- general purpose