Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS.
Chia-Wei PaiKen UchidaMunehiro TadaHiroki IshikuroPublished in: Microelectron. J. (2024)
Keyphrases
- low power
- high speed
- cmos technology
- single chip
- power consumption
- low cost
- nm technology
- low power consumption
- logic circuits
- vlsi architecture
- power dissipation
- digital signal processing
- low voltage
- ultra low power
- gate array
- mixed signal
- power reduction
- real time
- vlsi circuits
- wireless transmission
- high power
- image sensor
- analog to digital converter
- power management
- cmos image sensor
- design considerations
- image processing