Double-Latch Clocking Scheme for Low-Power I.P. Cores.

Claude Arm Jean-Marc Masgonty Christian Piguet

Published in: PATMOS (2000)

Keyphrases

low power
power consumption
low cost
high speed
power dissipation
single chip
wireless transmission
high power
flip flops
gate array
vlsi architecture
low power consumption
power reduction
digital signal processing
image sensor
mixed signal
vlsi circuits
energy efficiency
cmos technology
signal processor
nm technology