Design a Low-Power Scheduling Mechanism for a Multicore Android System.
Slo-Li ChuShiue-Ru ChenSheng-Fu WengPublished in: PAAP (2012)
Keyphrases
- low power
- single chip
- power consumption
- vlsi architecture
- high speed
- low cost
- logic circuits
- low power consumption
- digital signal processing
- cmos technology
- power dissipation
- ultra low power
- gate array
- wireless transmission
- high power
- design process
- image sensor
- scheduling algorithm
- power reduction
- mixed signal
- mobile devices
- real time