An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations.
B. HolandaR. PimentelJ. BarbosaR. CamarottiAbel G. Silva-FilhoL. JoãoViviane Lucy Santos de SouzaJ. FerrazM. LimaPublished in: IPDPS Workshops (2011)
Keyphrases
- matrix multiplication
- floating point
- message passing
- square root
- fixed point
- distributed memory
- field programmable gate array
- floating point arithmetic
- floating point unit
- matrix factorization
- sparse matrices
- parallel implementation
- instruction set
- computer vision
- fast fourier transform
- general purpose
- hardware implementation
- three dimensional