A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 µm CMOS.
Zhangming ZhuZheng QiuMaliang LiuRuixue DingPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2015)
Keyphrases
- analog to digital converter
- power consumption
- low cost
- low power
- random access memory
- power reduction
- synthetic aperture radar
- sar images
- general purpose
- high speed
- reconfigurable architecture
- power dissipation
- power management
- hardware implementation
- image sensor
- mixed signal
- nm technology
- chip design
- silicon on insulator
- delay insensitive
- automatic target recognition
- single chip
- power supply
- hardware and software
- signal processing