Design of R3TOS based reliable low power network on chip.
N. PoornimaSeetharaman GopalakrishnanTughrul ArslanT. N. PrabakarM. SanthiPublished in: EST (2017)
Keyphrases
- low power
- power dissipation
- low cost
- single chip
- power consumption
- low power consumption
- cmos technology
- high speed
- vlsi architecture
- network on chip
- digital signal processing
- logic circuits
- mixed signal
- ultra low power
- gate array
- design methodology
- parallel processing
- image processing
- power reduction
- design process
- real time