Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard.
Gustavo SanchezFilipo MórLuciano Volcan AgostiniCésar A. M. MarconPublished in: SBCCI (2017)
Keyphrases
- video coding standard
- hardware architecture
- video codec
- bit rate
- coding efficiency
- video coding
- rate distortion
- macroblock
- scalable video coding
- video compression
- coding method
- motion compensation
- mpeg avc
- motion compensated
- hardware implementation
- motion estimation
- motion vectors
- block size
- high coding efficiency
- inter frame
- mode decision
- compression efficiency
- video quality
- intra prediction
- visual quality
- discrete cosine transform
- intra coding
- variable block size
- low bit rate
- rate control
- image quality
- distributed video coding
- associative memory
- transform domain
- field programmable gate array
- digital video
- bitstream
- low complexity
- reference frame
- mode selection
- error resilience
- compression ratio
- subband
- video data
- low cost
- image compression
- coding scheme
- base layer
- enhancement layer
- video conferencing
- efficient implementation
- prediction error
- computer vision
- machine learning