Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction.
Atef IbrahimFayez GebaliPublished in: J. Signal Process. Syst. (2016)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- floating point
- power reduction
- high power
- single chip
- galois field
- vlsi circuits
- digital signal processing
- wireless transmission
- vlsi architecture
- low power consumption
- image sensor
- cmos technology
- cellular automata
- logic circuits
- hardware implementation
- hardware and software
- ultra low power
- image processing