A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS.
I-Ning KuZhiwei XuYen-Cheng KuanYen-Hsiang WangMau-Chung Frank ChangPublished in: CICC (2011)
Keyphrases
- low power
- power consumption
- wireless communication
- analog to digital converter
- nm technology
- cmos technology
- wireless transmission
- mixed signal
- single chip
- image sensor
- wireless networks
- short range
- computer simulation
- low voltage
- power reduction
- communication networks
- vlsi circuits
- power management
- wireless channels
- wireless sensor networks
- cmos image sensor
- high speed
- random access memory
- low cost
- low power consumption
- mobile communication
- wide dynamic range
- delay insensitive
- vlsi architecture
- digital signal processing
- physical layer
- cognitive radio
- power dissipation
- sensor data
- data streams
- parallel processing
- wifi