Low hardware complexity parallel turbo decoder architecture.
Zhongfeng WangYiyan TangYuke WangPublished in: ISCAS (2) (2003)
Keyphrases
- processing elements
- processing units
- hardware architecture
- parallel architecture
- hardware implementation
- multi core processors
- real time
- fpga implementation
- parallel hardware
- low cost
- computational complexity
- vlsi architecture
- vlsi implementation
- floating point arithmetic
- master slave
- software implementation
- parallel computation
- hardware software
- massively parallel
- low complexity
- shared memory
- parallel architectures
- pipelined architecture
- dedicated hardware
- hardware and software
- turbo codes
- multithreading
- parallel computers
- parallel processors
- hardware design
- parallel execution
- pipeline architecture
- heterogeneous systems
- parallel computing
- parallel processing
- floating point
- abstraction layer
- single instruction multiple data
- graphics processing units
- computing platform