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A 1.8mW 450-900MHz ±15ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS process.
Bhavin Odedara
Srikanth Bojja
Nitin Gupta
Igor Rapoport
Tony Ross
Alik Zelichenok
Published in:
NORCAS (2017)
Keyphrases
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noise tolerance
power consumption
high speed
cmos technology
noise tolerant
low power
feature vectors