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Performance improvement technique for synchronous circuits realized as LUT-based FPGAs.

Toshiaki MiyazakiHiroshi NakadaAkihiro TsutsuiKazuhisa YamadaNaohisa Ohta
Published in: IEEE Trans. Very Large Scale Integr. Syst. (1995)
Keyphrases
  • high speed
  • real time
  • image processing
  • significant improvement
  • neural network
  • lookup table
  • analog circuits
  • delay insensitive
  • logic synthesis