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A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.
Chen Kong Teh
Tetsuya Fujita
Hiroyuki Hara
Mototsugu Hamada
Published in:
ISSCC (2011)
Keyphrases
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power dissipation
power consumption
energy saving
cmos technology
single phase
low power
flip flops
energy efficiency
power management
circuit design
low voltage
air conditioning
input output
silicon on insulator
power supply
data center
energy consumption
control algorithm
high speed
neural network