Design of a low-power pulse-triggered flip-flop with conditional clock technique.
Guang-Ping XiangJi-Zhong ShenXue-Xiang WuLiang GengPublished in: ISCAS (2013)
Keyphrases
- low power
- power consumption
- power dissipation
- high speed
- cmos technology
- single chip
- low power consumption
- low cost
- vlsi architecture
- logic circuits
- digital signal processing
- gate array
- ultra low power
- mixed signal
- power reduction
- high power
- delay insensitive
- nm technology
- vlsi circuits
- intelligent control
- wireless transmission
- pattern recognition
- real time