Loop Scheduling for Transport Triggered Architecture Processors.
Perttu SalmelaRisto MäkinenPekka JääskeläinenJarmo TakalaPublished in: SoC (2006)
Keyphrases
- parallel processors
- scheduling problem
- multiprocessor systems
- heterogeneous computing
- list scheduling
- real time
- software architecture
- communication delays
- parallel machines
- parallel algorithm
- instruction scheduling
- scheduling strategy
- multi processor
- instruction set
- multithreading
- parallel architecture
- hardware implementation
- scheduling algorithm
- parallel processing
- high performance computing
- processor array
- resource allocation
- single processor
- flexible manufacturing systems
- management system
- memory access
- parallel computers
- information systems
- neural network