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3D floorplanning of low-power and area-efficient Network-on-Chip architecture.
Licheng Xue
Feng Shi
Weixing Ji
Haroon-Ur-Rashid Khan
Published in:
Microprocess. Microsystems (2011)
Keyphrases
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low power
cmos technology
network on chip
power consumption
vlsi architecture
power dissipation
low cost
high speed
mixed signal
single chip
multi processor
digital signal processing
routing algorithm
logic circuits
parallel processing
real time
image sensor