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A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector.
Liqun Feng
Qianxian Liao
Woogeun Rhee
Zhihua Wang
Published in:
A-SSCC (2023)
Keyphrases
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low voltage
cmos technology
flip flops
power line
design considerations
low power
power management
image sequences
power consumption
multiple input