A Systolic Array Architecture for Fast Decoding of One-Point AG Codes and Scheduling of Parallel Processing on It.
Shojiro SakataMasazumi KuriharaPublished in: AAECC (1999)
Keyphrases
- parallel processing
- parallel architecture
- systolic array
- reconfigurable architecture
- decoding algorithm
- computational power
- processing speed
- distributed processing
- scheduling problem
- error correction
- error control
- parallel computation
- parallel computers
- pc cluster
- processing units
- ldpc codes
- data flow
- parallel architectures
- data parallelism
- joint source channel
- parallel machines
- hardware implementation
- computer systems
- real time