Low Power Approximate Multiplier Using Error Tolerant Adder.
Jaeik ChoYoungmin KimPublished in: ISOCC (2020)
Keyphrases
- low power
- error tolerant
- logic circuits
- power consumption
- low cost
- high speed
- power dissipation
- graph matching
- single chip
- digital signal processing
- low power consumption
- subgraph isomorphism
- cmos technology
- pattern recognition
- mixed signal
- vlsi circuits
- hardware implementation
- power reduction
- association patterns
- data flow