An efficient FPGA architecture for hardware realization of hexagonal based motion estimation algorithm.
Muhammad MuzammilI. AliM. SharifK. A. KhalilPublished in: ICCE-TW (2015)
Keyphrases
- motion estimation algorithm
- low bit rate video coding
- motion compensation
- motion vectors
- motion estimation
- hardware implementation
- hardware architecture
- real time
- xilinx virtex
- pipelined architecture
- motion field
- block matching
- signal processing
- image processing
- rate distortion
- diamond search
- video coding
- image compression
- multiresolution
- multiscale
- neural network